(a) Field of the Invention
The present invention relates to a phase locked loop (PLL) circuit having a variable output frequency and, more particularly, to an improvement of such a PLL circuit to have an adjustable output frequency.
(b) Description of the Related Art
PLL circuits are used in a variety of equipment for generating a local oscillation frequency. The PLL circuit should have lower dimensions and be manufactured at a lower cost by, for example, reducing the number of electronic components thereof, in view that the PLL circuit is now installed in a mobile telephone or a GPS receiver which is ever requested to have a lower weight and smaller dimensions.
FIG. 1 shows a conventional PLL circuit, which includes a VCO 41, an N-divider 47 for dividing the output signal from the VCO 41 by a number of N to output an N-divided frequency signal, a reference frequency oscillator 46, an R-divider 45 for dividing the reference frequency by a number of R to output an R-divided frequency signal, a register 48 for storing the number N, a register 49 for storing the number R, a phase comparator 44 for comparing the phase of the N-divided frequency signal against the phase of the R-divided frequency signal, a charge pump 43 for receiving the result of the comparison from the phase comparator 44, and a loop filter (low-pass filter) 42 for passing the low-frequency component of the output from the charge pump 43 to generate a control voltage for the VCO 41. Thus, a negative feedback loop is formed in the PLL circuit.
The control signal from the loop filter 42 is substantially an integrated signal of the difference between the phase of the output from the N-divider 48 and the phase of the output from the R-divider 49. The output frequency from the VCO 41 is used as a local oscillation frequency signal during modulation or demodulation in a mobile telephone, for example.
The number N for dividing the output from the VCO 41 in the N-divider 47 is stored in the register 48 which receives the number N from a CPU disposed outside the PLL circuit.
A temperature-compensated crystal oscillator (TCXO) is generally used as the reference frequency oscillator 46. The number R for dividing the reference frequency in the R-divider 45 is stored in the register 49, which receives the number R from the external CPU. The numbers N and R are fed to the PLL circuit at the timing of a strobe signal.
The negative feedback loop of the PLL circuit allows the output oscillation frequency thereof to lock in a specified frequency defined by the reference frequency and the numbers N and R. More specifically, the output oscillation frequency fVCO from the VCO 41 is expressed by a function of the reference frequency ftCXO and the numbers N and R as follows:
fVCO=Nxc3x97ftXCO/Rxe2x80x83xe2x80x83(1). 
In general, the electronic components of the PLL circuit as described above can be integrated in a single LSI or LSI ship except for the VCO 41 and the reference frequency oscillator 46. The reference frequency oscillator 46 is not integrated in the LSI because the crystal oscillator cannot be installed in the LSI and an accurate frequency oscillator having a temperature-compensated output frequency cannot be manufactured without the crystal oscillator.
The VCO 41 is not integrated in the LSI in the prior art because the output frequency of the VCO significantly fluctuates due to the fluctuation of the ambient temperature and the variance or scattering of the characteristics of the components thereof and an adjustment of the output frequency in the LSI for compensating the temperature fluctuation etc. to obtain an accurate oscillation frequency is difficult to achieve. Thus, the VCO 41 is generally disposed in a dedicated package, adjusted to generate an accurate frequency range and have suitable temperature characteristics before installation, and then installed in the PLL circuit as a dedicated component disposed outside the LSI.
Some proposals were presented recently to install the VCO in a LSI. For example, a literature entitled xe2x80x9cA Low Phase Noise Monolithic VCO in SiGe BiCMOSxe2x80x9d by J. M. Mourant, J. Imboronen and Teksbury, in digest of papers, pp 65-68, 2000 IEEE Radio Frequency Integrated Circuits Symposium, describes the VCO shown in FIG. 2. FIG. 3 also shows a simplified equivalent circuit diagram of the VCO of FIG. 2. It is to be noted that FIG. 3 shows only a single end of the equivalent circuit of FIG. 2, which has the configuration of a typical differential oscillator generally used in a LSI.
The differential oscillator shown in FIG. 2 includes a plurality of pairs of pMOS transistors M00 and M10, M01 and M11, M02 and M12, and M03 and M13, wherein the sources and drains of each pair of pMOS transistors are connected together to form a serieal MOS capacitor pair. A control voltage CONT0, CONT1, CONT2 or CONT3 is applied to the common sources and drains of each transistor pair to vary the capacitance of each MOS capacitor, thereby forming a variable capacitance. These variable capacitances are shown by reference symbols C0, C1, C2 and C3 in FIG. 3.
A pair of diodes D04 and D14 having cathodes connected to the gates of the respective pMOS transistors and anodes connected together. A tune voltage signal TUNE having a potential lower than VCC is applied to the anodes of the diodes D04 and D14 to reverse-bias the diodes D04 and D14, thereby forming another capacitor pair having a variable capacitance, which is shown by a reference symbol C4 in FIG. 3.
A pair of bipolar transistors Q01 and 11 are provided each having a base applied with a voltage which divides the collector voltage of the other of the bipolar transistors Q01 and Q11 by a capacitor C05 or C15 and a reactor L12 or L02. Each of the bipolar transistors Q01 and Q11 thus has a negative resistance xe2x88x92R shown by the symbol Q1 in FIG. 3. A pair of coils L01 and L11 are connected between the power source line VCC and the gates of respective pMOS transistors, corresponding to the inductance L1 in FIG. 3.
In FIG. 3, the inductance L1 and the variable capacitances C0 to C4 form a parallel resonant circuit.
By achieving a negative resistance xe2x88x92R in the bipolar transistors which cancels the total resistance R of the resistance components of the variable capacitances C0 to C4 and the inductance L1 in FIG. 3, the parallel resonant circuit oscillates at a resonance frequency fOSC:
fOSC=1/{2xcfx80(L1xc3x97(C0+C1+C2+C3+C4))1/2}xe2x80x83xe2x80x83(2). 
Although the inductance L1 is realized by the coil installed in a LSI and thus cannot be controlled for the value, the resonance frequency fOSC can be varied by controlling the control voltages CONT0, CONT1, CONT2 and CONT3 applied to the variable capacitances C0 to C3 and a tune voltage TUNE applied to the variable capacitance C4.
Referring to FIG. 4, among other variable capacitances, the variable capacitance C4 reduces monotonically with the increase of the reverse-bias voltage due to the decrease of the depletion layer in the vicinity of the P-N junction. More specifically, the variable capacitance C4 decreases in inverse proportion to the square root of the reverse-bias voltage. The reverse-bias voltage is generated between the VCC voltage and the tune voltage TUNE which is applied to the anodes of the diodes D04 and D14 in FIG. 2. Thus, the resonance frequency decreases with the decrease of the tune voltage TUNE, and increases with the increase of the to tune voltage.
Each of the variable capacitances C0 to C3 shown in FIG. 4 changes abruptly between a lower capacitance Clow and a higher capacitance Chigh at a threshold voltage which resides between V1 and V0 of the bias voltage. These capacitances Clow and Chigh are stable for each of the variable capacitances C0 to C3. Accordingly, each of the variable capacitances can be controlled to have binary values by applying a gate voltage of V0 or V1 to the MOS capacitors.
The four MOS capacitor pairs have transistor sizes different from the transistor sizes of the other pairs, wherein the transistor size of the MOS capacitor having a specified order, for example M01 or M11, is double the transistor size of the MOS capacitor having an adjacent order, M00 or M10.
FIG. 5 shows the variable frequency range achieved by controlling the four-bit control signal applied to the variable capacitances C0 to C3 as well as controlling the tune voltage TUNE. The four control signals CONT0 to CONT3 correspond to the respective bits of a four-bit code or combination control signal, wherein CONT0 for the variable capacitance C0 corresponds to the least significant bit and CONT3 for the variable capacitance C3 corresponds to the most significant bit of the control signal. The variable frequency range shown by a double-arrow line for each code corresponds to the variable range of the variable capacitance C4. As shown in FIG. 5, by changing the selected code from xe2x80x9c0000xe2x80x9d to xe2x80x9c1111xe2x80x9d, the oscillation frequency fOSC can be changed stepwise for sixteen steps, with the tune voltage being controlled to change the oscillation frequency continually at each of the sixteen steps.
The above literature describes realization of the VCO which is installed in a LSI and has a variable oscillation frequency. In the described VCO, it is possible to control the output oscillation frequency by adjusting the tune voltage applied to the variable capacitance C4 and the control voltage applied to the variable capacitances C0 to C3. However, the literature is silent as to the techniques for detecting the deviation of the output oscillation frequency of the VCO from a specified frequency due to a temperature fluctuation or variance or scattering of the characteristics of the electronic components thereof, and for controlling the oscillation frequency at the specified frequency.
In view of the above, it is an object of the present invention to provide a practical PLL circuit which is capable compensating the deviation of the output frequency caused by a temperature fluctuation and variance or scattering of the characteristics of the components in the VCO, whereby the VCO can be integrated in a LSI constituting the PLL circuit substantially without loosing an accuracy of the output frequency.
The present invention provides a phase locked loop (PLL) circuit including: a reference frequency generator for generating a reference frequency signal having a reference frequency; a voltage controlled oscillator (VCO) including first and second variable capacitances, the VCO oscillating at an oscillation frequency based on the first and second variable capacitances; a first frequency divider for dividing the oscillation frequency by a first number to output a first frequency signal; a phase comparator for comparing a phase of the first frequency signal against a phase of the reference frequency signal to output a comparison result signal; a tune signal generation section for receiving the comparison result signal to output a tune signal, the tune signal controlling the first variable capacitance; a frequency control unit for generating a control signal controlling the second variable capacitances; and a lock-in detection section for detecting a lock-in of the oscillation frequency with respect to the reference frequency, the frequency control unit detecting, upon detection of a lock-in by the lock-in detection section, a deviation of the oscillation frequency from a normal oscillation frequency based on the tune signal, the first number and the reference frequency, the frequency control unit correcting the control signal based on the detected deviation.
In accordance with the PLL circuit of the present invention, the deviation of the output oscillation frequency, upon lock-in of the PLL circuit with respect to the reference frequency, can be corrected by adjusting the control signal for the second variable capacitance based on the tune signal detected by the frequency control unit. In addition, the VCO can be integrated in a LSI while allowing the compensation of the deviation in the output oscillation frequency caused by a temperature fluctuation or variance or scattering of the characteristics of the components of the LSI.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.